Planar technology is principally used currently for fabricating semiconductor surfaces. The level of integration that can be achieved on a semiconductor chip is limited by the size of the chip and by the structural fineness that is obtainable. The performance of a system which is realized using planar technology and which comprises a plurality of chips connected to one another is restricted by the number of possible connections between individual chips via connection contacts, the signal transmission speed that can be achieved via such connections (the so-called frequency performance) and also by the power consumption.
In order to overcome these restrictions, three-dimensional circuit arrangements have been suggested. In such arrangement, a plurality of chip planes are arranged one above the other in the third-dimensional circuit arrangements. The necessary electrical connections between the chip planes are produced by making direct contact.
For example, it has been suggested for producing three-dimensional integrated circuits, to deposit a further semiconductor layer on a substrate in which a plane of components has been produced. The semiconductor layer is recrystallized for instance by laser annealing. A further component plane is then realized in the recrystallized layer. The components produced in the substrate prior to the deposition of the further semiconductor are exposed during the recrystallization step to the thermal loading associated with the laser annealing, which leads to a very limited yield for the chips due to large numbers of defects which typically occur.
It has also been suggested to produce a three-dimensional integrated circuit by first producing the individual component planes separately from one another in different substrates. The substrates are then thinned to a few microns in thickness and are connected to one another with the aid of the wafer bonding method. For the electrical connection of the various component planes, the thin substrates are provided on their front and rear sides with contacts for subsequent interchip connections. This has the disadvantage that the thinned wafers have to be processed on both the front and rear sides. However, rear side processes are not provided in the standard planar technology. A number of handling problems remain unsolved in connection with this method. A further disadvantage of this particular method is that the functionality of the individual component planes cannot easily be tested before they are joined together, since individual components, but not completed circuits, are produced in each individual plane.
In addition, there have been suggestions for fabricating three-dimensional devices by creating the desired devices on individual semiconductor wafers prior to bonding them together to form the multilevel device. However, a major problem associated with this approach is that very precise alignment is required between the chips since the chips have already been built and are complete prior to the bonding. It is not entirely apparent how this precision alignment can be achieved on a practical basis. Furthermore, these processes require substantial thinning of one of the wafers by grinding or etching on the back side such as from a thickness of about 10-20 mils down to about 5 microns. This is an extremely different procedure to carry out. Moreover, great difficulties exist in controlling the thickness uniformity.
Accordingly, it would be desirable to provide three-dimensional multilayer devices that did not require the precise alignment as mentioned above.